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This paper presents a 0.6 V 10 bit successive approximation register(SAR) ADC design dedicated to the wireless sensor network application. It adopts a monotonic switching scheme in the DAC to save chip area and power consumption.The main drawback of the monotonic switching scheme is its large common mode shift and the associated comparator offset variation. Due to the limited headroom at the 0.6 V supply voltage, the conventional constant current biasing technique cannot be applied to the dynamic comparator. In this design, a common mode stabilizer is introduced to address this issue in low-voltage design. The effectiveness of this method is verified through both simulation and measurement results.Fabricated with 1P8M0.13 μm CMOS technology,the proposed SAR ADC consumes 6.3μ Wat1 MS/s from a 0.6V supply,and achieves 51.25dB SNDR at the Nyquist frequency and FOM of 21 fJ/conversion-step. The core area is only 120 300 μm2.
This paper presents a 0.6 V 10 bit approximation register (SAR) ADC design dedicated to the wireless sensor network application. It requires a monotonic switching scheme in the DAC to save chip area and power consumption. The main drawback of the monotonic switching scheme is its large common mode shift and the associated comparator offset variation. Due to the limited headroom at the 0.6 V supply voltage, the conventional constant current biasing technique can not be applied to the dynamic comparator. In this design, a common mode stabilizer is introduced to address this issue in low-voltage design. The effectiveness of this method is verified through both simulation and measurement results. Fabrics with 1P8M0.13 μm CMOS technology, the proposed SAR ADC consumes 6.3μ Wat1 MS / s from a 0.6V supply, and achieves 51.25 dB SNDR at the Nyquist frequency and FOM of 21 fJ / conversion-step. The core area is only 120 300 μm2.