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CCSDS空间图像压缩标准(CCSDS 122.0-B-1)的核心算法之一是三级二维小波变换,此变换适合用可编程逻辑电路实现。文章介绍了整数9/7小波变换的特点,提出了一种基于FPGA的二维变换快速实现结构,该方法利用FPGA内部Block RAM进行行暂存,实现了行列同时变换的效果,节省了内部寄存器资源,并获得了较高的数据吞吐率。在此基础上,文章还给出了两种适用于不同需求的多级变换架构,并通过仿真验证了其合理性。
One of the core algorithms of the CCSDS Spatial Image Compression Standard (CCSDS 122.0-B-1) is a three-dimensional two-dimensional wavelet transform suitable for use with programmable logic circuits. In this paper, the characteristics of integer 9/7 wavelet transform are introduced. A fast FPGA-based two-dimensional transform architecture is proposed. This method uses the internal block RAM of FPGA to perform temporary storage, which realizes the effect of simultaneous conversion of rows and columns, saves the internal registers Resources, and get a higher data throughput. On this basis, the article also gives two kinds of multi-level transformation architecture suitable for different requirements, and verifies its rationality through simulation.