目前,为了提高运算速度,大规模集成电路(LSI)乘法器主要采用并行运算方式,作为并行乘法器主要有将基本单元排列成规则的阵列式结构和为了追求高速度牺牲规则性的Booth算法、Wallace方法及Dadda方法等。另外,不采用阵列结构,而利用ROM来减少部分积加法网络级数的有Illinois大学研制的乘法器,但这种方案 At present, in order to increase the speed of operation, large-scale integrated circuit (LSI) multipliers mainly use the parallel operation mode. As the parallel multiplier, there are mainly an array structure in which basic cells are arranged in a regular manner and a Booth algorithm in pursuit of high-speed sacrificial regularity, Wallace method and Dadda method. In addition, there is a multiplier developed by the University of Illinois that does not use an array structure but uses ROM to reduce the number of partial product addition networks, but this solution