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针对当前工业相机和图像采集卡Camera Link标准接口需要使用专用集成电路才能实现的问题,提出采用最新Xilink的Virtex5系列现场可编程门阵列(field programmable gate array,FPGA),使用甚高速集成电路硬件描述语言(very high speed integrated circuits hardware description language,VHDL)编程实现Camera Link的信道链路解串器和帧获取器的逻辑时序和信号控制电路。通过Camera Link接口信号的误码率测试和采集信号的完整性实验,验证了系统设计原理的正确性和在高误码率条件下,正常采集图像的可靠性。因此本系统设计可以在相同系列FPGA之间进行有效的系统资源移植,简化硬件电路设计,节约一半以上的开发时间,提高大约75%的系统集成度。
In view of the problem that the current industrial camera and the image acquisition card Camera Link standard interface need to be realized by the application specific integrated circuit, a Virtex5 series field programmable gate array (FPGA) using the latest Xilink is proposed, and the very high speed integrated circuit hardware description Language (very high speed integrated circuits hardware description language, VHDL) program to implement the Camera Link channel deserializer and frame grabber logic timing and signal control circuit. Through the test of the bit error rate of the Camera Link interface and the integrity test of the collected signal, the correctness of the system design principle and the reliability of the normal acquisition image under the condition of high bit error rate are verified. Therefore, the system design can effectively transfer system resources between the same series of FPGAs, simplify the design of the hardware circuit, save more than half of the development time and improve the system integration by about 75%.