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时廷特性对于高性能的超大规模集成电路(VLSI)来讲是十分重要的。本文提出了一个新的时延驱动的布局方法。在初始布局中,我们提出了给线网加权的新方法,在迭代改善布局中提出了等位场的概念。实验结果表明:这是一种有效的时延驱动布局方法。
The timing characteristics are important for high performance Very Large Scale Integrated Circuits (VLSIs). This paper presents a new delay-driven layout method. In the initial layout, we propose a new method of weighting the wire mesh, and propose the concept of the equipotential field in the iterative improvement layout. The experimental results show that this is an effective method of delay-driven layout.