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NEC在研发55nmCMOS工艺技术中采用如下关键工艺:1.193nmArF浸润式光刻技术;2.高k介电质—HfSiON,实现高载流子迁移率,实际氧化膜厚度1.85nm;3.利用栅电极的工作函数来控制阈值电压,改变过去利用通道部门的杂质浓度来控制阈值电压。与65nmMOSFET相比,55nmMOSFET导通电流有大幅度
NEC R & D 55nmCMOS process technology used in the following key processes: 1.193nmArF immersion lithography technology; 2. High-k dielectric -HfSiON, to achieve high carrier mobility, the actual oxide film thickness of 1.85nm; 3. The use of gate electrode Of the work function to control the threshold voltage, change the past use of the channel part of the impurity concentration to control the threshold voltage. Compared with 65nmMOSFET, 55nmMOSFET conduction current has a substantial margin