文中对纳米技术下, 互连驱动的芯片级布图规划问题中的缓冲器规划问题进行了研究, 提出了基于空白区重分布(redistribution)的缓冲器规划算法; 布局中的空白区是指在布局中不被任何电路模块占用的闲置区域; 该算法充分利用布局中的空白区插入缓冲器. 在基于拓扑的布图规划表示中, 可以把电路模块和空白区相关联, 在相应区域内移动一些电路模块就可以达到重分布空白区的目的. 在进行空白区重分布的过程中, 给定布局的总面积和拓扑结构将维持不变. 通过重分布布局中的空白区, 可以增加满足时延约束的线网数目; 实验证实, 满足时延约束的线网数的增长率平均达到9%. In this paper, the buffer planning problem in chip-level layout planning driven by interconnected nano-technology is studied, and a buffer planning algorithm based on the blank area redistribution is proposed. The blank area in the layout is defined as An idle area in the layout that is not occupied by any circuit modules; this algorithm takes full advantage of the blank space inserted in the layout into the buffer. In topology-based layout planning representations, the circuit module can be associated with a blank area and moved within the corresponding area Some circuit modules can achieve the purpose of redistributing the blank area.While performing blank space redistribution, the total area and topology of a given layout will remain unchanged.While the blank space in the redistribution layout can be increased, The experimental results show that the growth rate of the number of line networks satisfying the delay constraint averages 9%.