An analytical drain current model on the basis of the surface potential is proposed for indium-gallium zinc oxide (InGaZnO) thin-film transistors (TFTs) with an independent dual-gate (IDG) structure. For a unified expression of carriers’ distribution for the sub-threshold region and the conduction region, the concept of equivalent flat-band voltage and the Lambert W function are introduced to solve the Poisson equation, and to derive the potential distribution of the active layer. In addition, the regional integration approach is used to develop a compact analytical current-voltage model. Although only two fitting parameters are required, a good agreement is obtained between the calculated results by the proposed model and the simulation results by TCAD. The proposed current-voltage model is then implemented by using Verilog-A for SPICE simulations of a dual-gate InGaZnO TFT integrated inverter circuit.