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随着无线通讯产业推动芯片集成度的不断提高,系统级封装(SIP)和多芯片组件(MCM)被更多采用,射频系统级芯片(RF-SOC)器件的良品测试已成为一大挑战。这些器件与传统的单晶片集成电路相比,具有更高的封装成本,并且由于采用多个晶片,成品率较低。其结果是进行晶圆上综合测试的成本远超过最终封装后测试器件的成本。此外,一些IC制造商销售裸晶片以用于另一些制造商的SIP和MCM中,这就要求发货的产品必须是良品。以蓝牙射频调制解调芯片为例,讨论了RF-SOC器件良品晶片(KGD)的测试难点和注意事项。对此样品,除了在晶圆上进行射频功能测试的难点,还有同时发射和测量数字、射频信号的综合问题。此外对被测器件(DUT)用印制线路板布线的难点,包括晶圆探针卡的设置及装配进行探讨。还介绍了选择探针测试台、射频晶圆探针卡和自动测试设备(ATE)时需考虑的因素。并以晶圆上测试的系统校正,包括难点和测试方法,作为结尾。这颗蓝牙射频调制解调芯片的实际测试数据也会被引用,以佐证和加深文章中的讨论。
As the wireless communications industry has driven the increasing integration of chips, system-in-package (SIP) and multi-chip modules (MCMs) have become more widely used. Quality testing of RF-SOC devices has become a challenge. These devices have higher packaging costs than conventional single-chip integrated circuits and offer lower yields due to the use of multiple dies. The result is that the cost of conducting a comprehensive test on the wafer far exceeds the cost of the final packaged test device. In addition, some IC manufacturers sell bare chips for use in other manufacturers’ SIP and MCM, which requires delivery of the product must be good. Taking Bluetooth RF demodulator chip as an example, the difficulties and precautions of the KGD test of RF-SOC device are discussed. This sample, in addition to the difficulty of RF functional testing on the wafer, as well as the simultaneous emission and measurement of digital, RF signal integration issues. In addition, the difficulty of wiring the DUT with the printed circuit board is discussed, including the setting and assembly of the wafer probe card. It also describes the factors to consider when choosing a probe test bench, a radio frequency wafer probe card, and an automatic test equipment (ATE). And to the wafer test system calibration, including the difficulties and test methods, as the end. The actual test data of the Bluetooth RF modem chip will also be quoted to support and deepen the discussion in the article.