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随着集成电路的飞跃发展,有可能用记忆元件来实现运算电路,本文提出利用ROM(Read only Memory)实现运算电路的一种方法。首先,提出各种并行计数器ROM的数学模型,其次,提出利用这种并行计数器ROM作为基本单元的多输入并行加法网络的构成算法,最后,对影响速度的因素进行讨论。 本文提出的多输入并行加法网络不但具有对于任何权(Weight)的输入信号直接进行高速处理的特点,而且,还具有结构非常简单、容易实现计算机辅助设计(CAD)的优点。因此,这种电路非常适合于高速乘法器、高速乘加器、高速卷积处理器,以及高速数字滤波器等信息处理用运算电路。
With the rapid development of integrated circuits, it is possible to use memory components to implement the operation circuit. In this paper, a method of using ROM (Read only Memory) to implement the operation circuit is proposed. First of all, a mathematical model of parallel counter ROM is proposed. Secondly, the composition algorithm of multi-input parallel adder network using this parallel counter ROM as the basic unit is proposed. Finally, the factors affecting the speed are discussed. The multi-input parallel addition network proposed in this paper not only has the advantages of direct high-speed processing of any weight input signal, but also has the advantages of simple structure and easy realization of computer aided design (CAD). Therefore, this circuit is ideal for information processing such as high-speed multipliers, high-speed multipliers, high-speed convolution processors, and high-speed digital filters.