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在分析串行结构CRC生成算法的基础上,提出了一种高效的8bit并行CRC-32校验码生成算法。利用该算法在特定FPGA芯片上实现了任意字节的CRC-32校验码的生成模块,该模块仅占用93个逻辑单元,最高数据吞吐量可达2400Mbps。
Based on the analysis of serial structure CRC generation algorithm, an efficient 8bit parallel CRC-32 code generation algorithm is proposed. By using this algorithm, an arbitrary byte CRC-32 code generation module is implemented on a specific FPGA chip, which occupies only 93 logical units and the maximum data throughput can reach 2400 Mbps.