在0．18μm及其以下的晶体管中，如果半导体生产厂不积极进行内建可靠性设计，就不能向用户提供更大规模的LSI。在0．35μm以上的晶体管中，无论是nMOS还是pMOS都是采用把概电极掺杂在n+中的n－n栅工艺。虽然有工艺简单的优点，但是，也存在pMOS的阈值电压控制难的缺点。为了把 In 0.18μm and below transistors, if the semiconductor manufacturer is not actively built-in reliability design, you can not provide users with larger LSI. In 0.35μm or more transistors, both nMOS and pMOS are n-n gate technology used to dope electrode in n +. Although the advantages of simple process, but there is also the threshold voltage pMOS difficult to control the shortcomings. In order to put