提出了基于双比特算法的新型除法器及其VLSI实现结构 .与MIPS微处理器中的除法器相比 ,它的平均执行周期减少了 5 2 5 % ,而其最大延时几乎不变 ,仅晶体管数目增加了 6 0 % .仿真结果表明 ,在相同的运算能力下 ,其功耗仅为MIPS中除法器的 11 3% . A novel divider based on double-bit algorithm and its VLSI implementation structure are proposed.Compared with the divider in MIPS microprocessor, the average execution period is reduced by 52.5% while its maximum delay is almost unchanged, only The number of transistors has increased by 60%. The simulation results show that the power consumption is only 11 3% of the divider in MIPS with the same computing power.