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目前所设计的系统级芯片 (SOC)包含有多个 data- path模块 ,这使得 data- path成为整个 G大规模集成电路 (GSI)设计中最关键的部分 .以往的布图理论及算法在许多方面已不能满足 data- path布图设计的需要 ,这主要是由于传统的布图工具没有考虑 data- path所特有的电路结构特点 . Data- path具有规整的位片结构 ,具有很高的性能指标要求 ,如对于时延、耦合效应和串扰等性能都有严格的要求 .此外 ,data- path中还存在大量成束状结构的 BUS线网 .文中提出了 data- path布图设计所面临的挑战 .从介绍 data- path布图的基本问题入手 ,重点分析了 data- path布图设计中的关键技术 ,并在讨论已有研究工作的基础上针对不同的布图阶段提出了可行的技术路线与设想 .
So far, the system-on-chip (SOC) has many data-path modules, which make data-path the most critical part in the design of the G-GSI.In the past, many layout theory and algorithms Data-path layout design can not meet the needs of the data, which is mainly due to the traditional layout tools did not consider the specific data-path circuit structure. Data-path has a regular bit-slice structure, with high performance indicators Requirements, such as the delay, coupling effects and crosstalk performance are stringent requirements.In addition, the data-path there are still a large number of bundled structure BUS network.This paper presents the data- path layout design challenges Starting with the introduction of the basic problems of data-path layout, the key technologies in the design of data-path layout are analyzed emphatically. Based on the discussion of the existing research work, some feasible technical routes are proposed according to different layout stages Imagine.